This invention relates to a semiconductor integrated circuit device and, more particularly, to a delay-locked loop (DLL) and a semiconductor integrated circuit device equipped with the DLL.
A DDR (Double Data Rate)-I-SDRAM (Synchronous Dynamic Random-Access Memory) is designed to perform data transfer at a transfer rate of 200 to 300 Mbps (megabits per second) with respect to an input clock having a frequency of 100 to 166 MHz. Design specification is such that data input is synchronized to both rising and falling edges of an input clock signal. The desired specifications can be achieved with a DLL of minimal structure by passing the entered clock through a single delay line as is.
FIG. 18 is a diagram illustrating an example of a DLL(Delay Locked Loop) in compliance with DDR specifications, and FIG. 19 is a diagram illustrating the timing operation of this DLL.
Referring to FIG. 18, the DLL 3A is equipped with an input buffer 1, the inputs to which are mutually complementary clock signals CLK and CLKB transmitted in a differential mode, for outputting a clock signal CLK1 of single-phase (single-end) mode, and includes a delay line 31 for delaying and outputting the clock signal CLK1 input thereto from the input buffer 1. The delay line 31 outputs the delayed signal from one output tap selected from among a plurality of output taps (not shown) whose delay times differ from one another, thereby making it possible to change the delay time.
Provided are a multiplexer (MUX) 4, which receives two items of data read out of a memory-cell array (not shown), for selecting the data using the signal CLKOE, which is output from the delay line 31, as a clock for data output; an output buffer 5, which receives the output signal of the multiplexer 4, for delivering this signal to a data output terminal as a data output signal DQj; a dummy multiplexer (MUX) 36 having a delay time identical with that of the multiplexer 4 and having the output signal CLKOE of the delay line 31 input thereto as a selection signal for outputting a HIGH- or LOW level signal; a dummy buffer 37 having a delay time identical with that of the output buffer 5 and having the output of the dummy multiplexer 36 input thereto for outputting complementary clock signals RCLK and RCLKB; a dummy buffer 38 having a delay time identical with that of the input buffer 1 and having the clock signals RCLK, RCLKB, which have been transmitted in the differential mode, input thereto for outputting a single-end clock signal CLKFBI; a phase detector 33, to which the output signal CLK1 of the input buffer 1 and the output signal CLKFBI of the dummy buffer 38 are input, for detecting the phase difference between the signals CLK1 and CLKFBI; and a counter 34 for counting up or down in accordance with phase lead/lag depending upon the result of phase detection by the phase detector 33. Fixed values of the HIGH level (VDD potential) and LOW level (VSS potential) are supplied as data to the dummy multiplexer 36, which selects and outputs one of these values using the entered signal CLKOE as the selection signal.
In the DLL 3A, the output tap of the delay line 31 is changed over based upon the output signal of the counter 34 in such a manner that the output clock signal CLK1 of input buffer 1 and output signal CLKFBI of dummy buffer 38 will agree, thereby adjusting the delay time of the DLL. As shown in the timing chart of FIG. 19, the output signal DQj of the DDR-SDRAM is locked (synchronized) to the clock CLK.
Referring to FIG. 19, the timing of the rising edge of signal CLKOE is delayed by delay time td0 of the delay line 31 relative to the timing of the rising edge of output clock CLK1 of input buffer 1 [see arrow (1) in FIG. 19]. The rising edge of the signal CLKFBI is delayed relative to the timing of the rising edge of signal CLKOE by time td1+td2+td3, which is the sum of delay times td3, td2, and td1 of dummy multiplexer 36 and buffers 37 and 38, respectively [arrow (3) in FIG. 19].
Control is exercised in such a manner that the timing of the rising edge of signal CLKFBI will coincide with the timing (delayed by the delay time td1 of the input buffer 1 relative to the starting timing of the cycle of clock CLK) of the rising edge of clock CLK1 prevailing one cycle after the clock CLK from which the present signal CLKFBI originates.
Consequently, the timing of the rising edge of signal CLKFBI becomes
tCK+td1
with the timing of the rising edge of input clock CLK (clock cycle=tCK) serving as the reference.
Accordingly, the timing of the rising edge of clock CLKOE becomes
tCK+td1xe2x88x92(td1+td2+td3)=tCKxe2x88x92td2xe2x88x92td3
In the data output propagation path through the multiplexer 4, the propagation delay time from the rising edge of signal CLKOE to the output, of multiplexer 4 is td3 and the propagation delay time of the output buffer 5 is td2 [arrow (4) in FIG. 19] and therefore the output timing of the data output signal DQj is
(tCKxe2x88x92td2xe2x88x92td3)+td3+td2=tCK
In other words, the timing of the rising edge of clock CLK (the starting point of the clock cycle) and the timing at which the data output signal DQj is delivered agree.
Similarly, the timing of the falling edge of signal CLKOE is delayed by delay time td0 of the delay line 31 relative to the timing of the falling edge of output clock CLK1 of input buffer 1 [see arrow (2) in FIG. 19]. The timing of the falling edge of the signal CLKFBI lags behind the timing of the rising edge of this signal by the pulse width of clock CLK1 [arrow (5) in FIG. 19]. The next data output signal DQj is delivered at the falling edge of the signal CLKOE, and the timing thereof coincides with the timing of the falling edge of clock CLK (the rising edge of clock CLKB). The DLL 3A having the construction shown in FIG. 18 is a circuit that adjusts and matches the phases of the input clock and output data and may also be referred to as an xe2x80x9cinput/output-compensating DLLxe2x80x9d.
The specifications of a DDR-II-SDRAM are such that an even higher speed is attained, namely a clock frequency of 200 to 300 MHz (a data transfer rate of 400 to 600 mbps). In order to improve the operating margin of a memory controller, a design (Duty Cycle Correction, abbreviated to xe2x80x9cDCCxe2x80x9d) that synchronizes the input clock CLK to phases of 0 and 180 degrees is currently under study.
As shown by way of example in FIG. 20, a DLL in compliance with the specifications of a DDR-II-SDRAM is constituted by a total of four delay lines, namely a delay line (which corresponds to delay line 31 in FIG. 18) for 0xc2x0 propagation as well as a delay line 32 for 180xc2x0 propagation and two delay lines 21 and 22 for generating a 180xc2x0 phase difference. In other words, this DLL circuit has a DLL 2B for generating tCK/2 and a DLL 3B for input/output compensation.
Referring to FIG. 20, the tCK/2 generating DLL 2B includes the delay line 21, which receives the clock signal CLK1 from the input buffer 1 having the clocks CLK and CLKB applied thereto, for varying the delay time of its output signal CLKHF by changing over the output tap; the delay line 22, which receives the clock signal CLKHF from the delay line 21, for varying the delay time of its output signal CLKFBH by changing over the output tap; a phase detector 23, which receives the clock CLK1 and the output signal CLKFBH of delay line 22, for detecting the phase difference between these two signals; and a counter 24 for counting up or down in accordance with phase lead/lag depending upon the result of phase detection by the phase detector 23. The output taps of the delay circuits 21 and 22 are selected in such a manner that the timings of the rising edges of the signals CLKFBH and CLK1 (CLK1 one cycle later than the cycle of clock CLK1 at which the signal CLKFBH was generated, where the clock period of the clock CLK is tCK) input to the phase detector 23 will coincide. That is, if the timing of the rising edge of signal CLKFBH obtained by delaying the clock signal CLK1 by td in delay line 21 and further by td in delay line 22 coincides with the timing of the rising edge of clock signal CLK1, then we have
td+td=tCK
as a result of which the delay time td of each of the delay lines 21 and 22 is
td=tCK/2.
The timing of the rising edge of clock signal CLKHF output from the tCK/2 generating DLL 2B is delayed by one-half of the clock cycle tCK relative to the timing of the rising edge of clock signal CLK1, whereby a phase difference of 180xc2x0 is produced.
The input/output-compensating DLL 3B includes the delay line 31, which receives the clock signal CLK1 that is the output of the input buffer 1, for varying the delay time of its output signal OUTR by changing over the output tap; the delay line 32, which receives the output signal CLKHF of the delay line 21, for varying the delay time of its output signal OUTF by changing over the output tap; a multiplexer (MUX) 35B, which receives the outputs OUTR and OUTF of the delay lines 31 and 32, for producing the output signal CLKOE whose pulse rising-edge and falling-edge timings are decided by the timings of the rising edges of signals OUTR and OUTF; the multiplexer (MUX) 4, which receives the output signal CLKOE (data-output clock) of the multiplexer 35B as a selection signal, for selectively outputting two items of data per clock cycle of the clock CLK; the output buffer 5, which receives the output of the multiplexer 4, for outputting this signal as signal DQj; the dummy multiplexer 36 having a delay time identical with that of the multiplexer 4 and having the output signal CLKOE of multiplexer 35B input thereto; the dummy buffer 37 having a delay time identical with that of the output buffer 5 and having the output of the dummy multiplexer 36 input thereto for outputting complementary clock signals RCLK and RCLKB; the dummy buffer 38 having a delay time identical with that of the input buffer 1 and having the complementary signals RCLK and RCLKB input thereto for outputting the single-end clock signal CLKFBI; the phase detector 33, which receives the output signal CLK1 of the input buffer 1 and the output signal CLKFBI of the dummy buffer 38, for detecting the phase difference between the signals CLK1 and CLKFBI; and the counter 34 for counting up or down depending upon the output of the phase detector 33. The output taps of the delay lines 31 and 32 are changed over by the output of the counter 34, whereby delay time is adjusted. The HIGH and LOW fixed values are input as data to the dummy multiplexer 36, which selects and outputs one of these values using the entered signal CLKOE as the selection signal.
FIG. 21 is a diagram useful in describing the timing operation of the circuit illustrated in FIG. 20. The operation of the circuit depicted in FIG. 20 will be described with reference to FIG. 21.
The delay line 31, which receives the output clock signal CLK1 of delay line 21, outputs the signal OUTR obtained by delaying the clock signal CLK1 by the time td0 [see arrow (2) in FIG. 21]. The delay line 32, which receives the signal CLKHF obtained by delaying the clock CLK1 by tCK/2 [see arrow (1) in FIG. 21], produces the output OUTF obtained by delaying the signal CLKHF by td0 [arrow (3) in FIG. 21]. The output signal CLKOE of multiplexer 35B rises to the HIGH level [arrow (4) in FIG. 21] at the rising edge of signal OUTR and falls to the LOW level [arrow (5) in FIG. 21] at the rising edge of signal OUTF.
Selection of data in the multiplexer 4 is carried out at the rising and falling edges of the signal CLKOE, and the output of signal DQj delivered from the output buffer 5 is timed to occur in one-half cycle units of cycle tCK of clock signal CLK. This operation will now be described.
The clock CLKOE, which is the data output clock delivered from the multiplexer 35B, rises (at the timing of the rising edge of signal OUTR) upon being delayed by delay time td0 of delay line 31 from the rising edge of output clock CLK1 of input buffer 1; it has a pulse width of
td0+tCK/2xe2x88x92td0=tCK/2
The timing of the falling edge of signal CLKOE is
tCK/2+td0
from the rising edge of the output clock CLK1 of input buffer 1 (i.e., the timing is the rising edge of signal OUTF).
The rising edge of the signal CLKFBI is delayed relative to the timing of the rising edge of signal CLKOE by time td1+td2+td3, which is the sum of delay times td3, td2, td1 of dummy multiplexer 36 and buffers 37, 38, respectively [arrow (6) in FIG. 20].
Control is exercised in such a manner that the timing of the rising edge of signal CLKFBI will coincide with the timing of the rising edge of clock CLK1 prevailing n cycles (three cycles in FIG. 21) after the clock CLK from which the present signal CLKFBI originates (where CLK1 is delayed by the delay time td1 of input buffer 1 relative to the starting timing of the cycle of clock CLK). Consequently, the timing of the rising edge of signal CLKFBI becomes
ntCK+td1
with the timing of the rising edge of input clock CLK (clock cycle=tCK) serving as the reference.
Accordingly, the timing of the rising edge of clock CLKOE becomes
ntCK+td1xe2x88x92(td1+td2+td3)=ntCKxe2x88x92td2xe2x88x92td3
In the data output propagation path through the multiplexer 4, the propagation delay time from the rising edge of signal CLKOE to the output of multiplexer 4 is td3 and the propagation delay time of the output buffer 5 is td2 [arrow (7) in FIG. 21]. The output timing of the data output signal DQj, therefore, is
(ntCKxe2x88x92td2xe2x88x92td3)+td3+td2=ntCK
In other words, the starting point of the clock cycle of clock CLK (the timing of the rising edge of clock CLK) and the timing at which the data output signal DQj is delivered agree.
Further, the timing of the falling edge of signal CLKOE lags behind the timing of the rising edge thereof by tCK/2, so that the timing of the falling edge of signal CLKOE is
(ntCKxe2x88x92td2xe2x88x92td3+tCK/2)+td3+td2=ntCK+tCK/2
Accordingly, the output timing of the second data output signal DQj is tCK/2 from the starting point of the clock cycle of clock signal CLK.
In the data output path through the multiplexer 4, the propagation delay time from the rising edge is td3, and the propagation delay time of the output buffer 5 is td2 [arrow (9) in FIG. 21], and hence we have as the output timing of the second data output signal DQj,
(ntCKxe2x88x92td2xe2x88x92td3+tCK/2)+td3+td2=ntCK+tCK/2
Accordingly, the output timing of the second data output signal DQj is at the timing which is tCK/2 delayed from the starting point of clock cycle of the clock CLK.
Thus, as shown in FIG. 21, duty correction of clocks CLK/CLKB the duty ratios of which differ by 50% is carried out and an output operation. having a data window of 50% is performed.
The delay lines 21, 22, 31,and 32 have a structure of the kind shown in FIG. 14. Each delay line has taps D1, D2 and D3, and switches (tri-state inverters or CMOS transfer gates) are connected between respective ones of the taps and an output node. One switch is turned on and the others are turned off by tap control signals C1, C2 and C3, whereby the tap corresponding to the ON switch is selected.
The duty cycle correction function will be described in greater detail. As mentioned above, the tCK/2 generating DLL 2B of FIG. 20 acts as a duty correction circuit (DCC).
Reference will be had to FIG. 17 to describe a system configuration, which is driven by a clock signal supplied from a clock generating source 52, having a plurality of clock-synchronization-type memories 51l to 51n that output read-out data DQj to a memory controller 50 in sync with the clock. FIG. 16 is a diagram useful in comparing and describing a case devoid of the DCC function and a case having the DCC function.
Even if a near-end clock signal CLK from clock generating source 52 has a duty ratio of 50%, the duty ratio of the clock signal at the far end will deviate from 50% owing to the presence of clock skew (xcex1).
If the data window of DQj at the near end fluctuates by 62 % in the case of a clock-synchronization-type memory not having the DCC function, then the data window of data DQj at the far end will exhibit a fluctuation of 50% xc2x1(xcex1+xcex2) owing to the presence of clock skew.
By contrast, with a clock-synchronization-type memory having the DCC function, the duty ratio of the clock is made 50% and the duty window of DQj at the near end becomes 50%. Even if the data window exhibits a fluctuation of xcex2%, the data window of data DQj at the far end will exhibit a fluctuation of 50%xc2x1xcex2 and the effects of clock skew can be eliminated or reduced.
According to the specifications of a DDR-II-SDRAM, the operating cycle is 3.3 ns, which is half that of a DDR-I-SDRAM, and the pulse width of the clock signal that propagates through the interior of the DLL of a delay line or the like is a maximum 1.7 ns. This is a small value that is half that of the DDR-I-SDRAM. Consequently, if the threshold value of a transistor constituting the delay line of the DLL rises and the waveform of a rising edge becomes deformed, the output signal will begin to decay before it reaches its peak. This makes it difficult to maintain a high timing precision.
In addition, a DDR-II-SDRAM is provided with four delay lines, so that the delay-line operating current is four times the delay-line current of a DDR-I-SDRAM. The result is an increase in power consumption.
Next, assume that the delay line having the structure shown in FIG. 14 has cascade-connected inverters INV11, INV12, . . . to provide the output taps. In FIG. 14, two serially connected inverters compose a unit delay line. Tri-state inverters INV17, INV18, and INV19 (or transfer gates) connected between respective ones of the taps and the output node are output-enabled or output-disabled (the latter meaning that the output attains a high impedance) in accordance with the logic values of the tap selection signals C1, C2, and C3, respectively, from a counter. Output taps are thus selected by the tap selection signals C1, C2, and C3 and the clock signal is output from the tap selected.
In FIGS. 18 and 20, the phase detector 33 (23) detects the lead/lag phase relationship between the clock signal CLKFBI (CLKFBH) and the reference clock signal CLK1 and updates the counter 34 (24). In addition, in order to prevent erroneous decisions from being made before and after the device is powered down, for example, the phase detector 33 (23) performs detection based upon the timing of signal CLKFBI (CLKFBH). If the tap is changed over at the timing at which the signal that propagates through the interior of the delay line is output from the tap, a hazard or abnormal pulse may be produced in the data-output clock signal CLKOE or a malfunction may occur. The reason for this is that the count in counter 34 (24) is updated and the tap is changed over at the transition timing of the signal CLKFBI (CLKFBH).
FIG. 15 is a diagram useful in describing operation at tap changeover of the delay line shown in FIG. 14. If, during the time a signal advances from D1 to D2, as shown in FIG. 15, signals C1 and C2 of tap selection signals C1, C2, and C3 change from the High to the LOW level and from the Low to the HIGH level, respectively, and tap D1 is changed over to tap D2, then a hazard will be produced in the output signal.
With regard to the delay line 31 (32) in the input/output-compensated DLLs 3A, and 3B shown in FIGS. 18 and 19, the tap will be changed over during propagation of the signal through the delay line 31 (32) if signal propagation takes, e.g., 2 to 3 ns and the clock cycle is short. Further, with the tCK/2 generating DLL 2B of FIG. 20, tap changeover is performed while the signals CLK1 and CLKHF of the first half of the clock cycle propagate through the delay lines 21 and 22. As a consequence, a hazard is produced in the output signal of the delay line.
Accordingly, it is an object of the present invention to provide a DLL and a semiconductor integrated circuit device of reduced power consumption suited for use in equipment that complies with DDR-II specifications.
Another object of the present invention is to provide a DLL and a semiconductor integrated circuit device in which the occurrence of hazards at the time of tap changeover is suppressed, thereby preventing a deviation in output timing as well as malfunction.
In accordance with one aspect of the present invention, the above and other objects of the invention are attained by providing a delay-locked loop device for adjusting delay times of serially connected first and second delay lines in such a manner that a signal obtained by delaying an input signal by the first and second delay lines is in phase with the input signal, thereby outputting, from the first delay line, a signal that is the result of delaying the input signal by one half cycle of the input signal, comprising:
a frequency dividing circuit for performing frequency division of the input signal, an output signal from said frequency dividing circuit being delayed by said first and second delay lines; and first delay adjustment means for outputting a control signal for adjusting the delay times of said first and second delay lines in such a manner that the output signal of said frequency dividing circuit and an output signal of said second delay line are in phase.
Further, in accordance with the present invention, there is provided a delay-locked loop device comprising, in addition to the above-described elements, a second delay-locked loop for generating a data-output clock signal based upon the input signal and supplying the data-output clock to a multiplexer that selectively outputs multiple items of data, the second delay-locked loop including: a third delay line, to which the output signal of the frequency dividing circuit is input, for outputting a first signal by delaying this output signal; a fourth delay line, to which an output signal of the above-described delay-locked loop device is input, for outputting a second signal by delaying this output signal; a circuit, to which the first and second signals from the third and fourth delay lines, respectively, are input, for outputting, as the data-output clock, a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the first and second signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones of the first and second signals; and second delay adjusting means for outputting a control signal for adjusting delay times of the third and fourth delay lines in such a manner that a signal obtained by delaying the data-output clock by at least a delay time of the multiplexer will be in phase with the input signal.
Furthermore, the delay-locked loop device according to the present invention may further include a first latch circuit for supplying the control signal from the first delay adjusting means to the first and second delay lines upon latching the control signal by the output signal of the first delay line.
Furthermore, the delay-locked loop device according to the present invention may further include a second latch circuit for supplying the control signal from the second delay adjusting means to the third and fourth delay lines upon latching the control signal by the data-output clock.
In accordance with another aspect of the present invention, the above and other objects of the invention are attained by providing a semiconductor integrated circuit device comprising an input buffer to which a clock signal is input; a frequency dividing circuit, to which the clock signal output from the input buffer is input, for halving frequency of the input clock signal and outputting a frequency-divided clock; a first delay-locked loop circuit that includes a first delay line, to which the frequency-divided clock output from the frequency dividing circuit is input, for outputting a delayed signal from an output tap selected from among a plurality of output taps, a second delay line, to which an output signal of the first delay line is input, for outputting a delayed signal from an output tap selected from among a plurality of output taps, a first phase detector for detecting a phase difference between the frequency-divided clock and an output of the second delay line, and a first counter for counting up or down depending upon an output from the first phase detector and outputting a signal that changes over the output taps of the first and second delay lines; and a second delay-locked loop circuit that includes a third delay line, to which the frequency-divided clock output from the frequency dividing circuit is input, for outputting a delayed signal from an output tap selected from among a plurality of output taps, a fourth delay line, to which an output signal of the first delay line is input, for outputting a delayed signal from an output tap selected from among a plurality of output taps, a first multiplexer, to which output signals of the third and fourth delay lines are input, for outputting a signal in which rising and falling edges of a pulse are decided by timings of rising edges of output signals from respective ones of the third and fourth delay lines, and in which rising and falling edges of a succeeding pulse are decided by timings of falling edges of output signals from respective ones of the third and fourth delay lines, a dummy third multiplexer, receiving and outputting the output signal of the first multiplexer and an having a delay time identical with that of a second multiplexer, said second multiplexer selecting data using the output signal of the first multiplexer as a selection signal, a dummy first buffer to which an output of the third multiplexer is input and having a delay time identical with that of an output buffer, a dummy second buffer to which an output of the first buffer is input and having a delay time identical with that of the input buffer, a second phase detector for detecting a phase difference between the output of the input buffer an output of the dummy second buffer, and a second counter for counting up or down depending upon an output from the second phase detector and outputting a signal that changes over the output taps of the third and fourth delay lines; the output signal of the first multiplexer being input to the second multiplexer, the second multiplexer selecting one of multiple items of data input thereto, and the output buffer, to which an output signal of the second multiplexer is input, outputting this signal from an output terminal.
A semiconductor integrated circuit device in accordance with a further aspect of the present invention, comprises an input buffer to which a clock signal is input; a first delay-locked loop circuit that includes a first delay line, to which the clock signal output from the input buffer is input, for outputting a delayed signal from an output tap selected from among a plurality of output taps, a second delay line, to which an output signal of the first delay line is input, for outputting a delayed signal from an output tap selected from among a plurality of output taps, a first phase detector for detecting a phase difference between the output clock from the input buffer and an output of the second delay line, a first counter for counting up or down depending upon an output from the first phase detector and outputting a signal that changes over the output taps of the first and second delay lines, and a first aligner, to which the output signal of the first delay line is input as a latch signal, for latching the output of the first counter and supplying the output to the first and second delay lines; and a second delay-locked loop circuit that includes a third delay line, to which the clock signal output from the input buffer is output, for outputting a delayed signal from an output tap selected from among a plurality of output taps, a fourth delay line, to which the output signal of the first delay line is input, for outputting a delayed signal from an output tap selected from among a plurality of output taps, a first multiplexer, to which output signals of the third and fourth delay lines are input, for outputting a signal in which rising and falling edges of a pulse are decided by timings of rising edges of output signals from respective ones of the third and fourth delay lines, and in which rising and falling edges of a succeeding pulse are decided by timings of falling edges of output signals from respective ones of the third and fourth delay lines, a second multiplexer, to which the output signal of the first multiplexer is input, for selecting data using the output signal of the first multiplexer as a selection signal, a dummy third multiplexer having a delay time identical with that of the second multiplexer, a dummy first buffer to which an output of the third multiplexer is input and having a delay time identical with that of an output buffer, a dummy second buffer to which an output of the first buffer is input and having a delay time identical with that of the input buffer, a second phase detector for detecting a phase difference between the output of the input buffer an output of the dummy second buffer, a second counter for counting up or down depending upon an output from the second phase detector and outputting a signal that changes over the output taps of the third and fourth delay lines, and a second aligner, to which the output signal of the second multiplexer is input as a latch signal, for latching the output of the second counter and supplying the output to the third and fourth delay lines; the output signal of the first multiplexer being input to the second multiplexer, the second multiplexer selecting one of multiple items of data input thereto, and the output buffer, to which the output signal of the second multiplexer is input, outputting this signal from an output terminal.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.